Digital Circuit Synthesis Using Universal Set of CMOS MVL Gates

The synthesis of digital circuits is generally performed in two level logic switching algebra. But if we increase the representation domain from two level logic (N=2) to N>2 then the design of Multiple Valued Logic (MVL) digital circuits is possible. Interconnections play an important role in deep submicron designs as they affects power and area. Due to the requirement of interconnections the design of binary logic is limited. In modern SoC designs,the interconnection is becoming a major problem which can be solved using MVL interconnection. Thus reduction in the area along with advantage of being able to easily interface with traditional binary logic circuits are the benefits of MVL digital circuits. A universal set of MVL CMOS gates can be used to synthesize and implement any MVL digital circuit. The lack of existing integrated circuits to implement the universal set of MVL gates is one of the major drawbacks. To overcome this issue, the design and implementation of a universal set of Integrated Circuits gates using CMOS 180nm technology is proposed which includes: Maximum (MAX), extended AND operatorseAND1, eAND2, eAND3, Successor (SUC) to synthesize any MVL circuit. The proposed gates allows designing of any MVL digital circuit by utilizing the knowledge coming from the binary circuits and extending it for the synthesis of MVL digital circuit. Keywords—Multiple valued logic, SoC